The present invention relates to fabrication of integrated circuits. In particular, this invention relates to methods of etching thin films of refractory metals, metal silicides, polycides, and metal/polysilicon sandwich structures by plasma or reactive ion etching to form interconnects for VLSI integrated circuits.
As MOS integrated circuit complexity has increased, the circuit performance gains which normally result from the decreases in individual circuit component size with scaling have begun to be limited by the RC time constant characteristics of the long interconnects required to interconnect the increased number of circuit components. To reduce the resistance component of these long length interconnects, integrated circuit manufacturers have been turning to refractory metals, refractory metal silicides, and polysilicon/refractory metal silicide composite films (referred to as polycides) to replace the polysilicon conventionally used for gate level interconnects. Such materials offer interconnect sheet resistances of one to three ohms per square, compared to ten ohms per square or more for polysilicon alone.
However, this use of new materials has introduced new processing problems. Dry etching (plasma or reactive ion etching) has long been the accepted method of etching patterns in polysilicon to provide integrated circuit gate and/or interconnect levels. The chemistry to provide anisotropic etching of polysilicon with good differential etch rate with respect to silicon dioxide is widely known. However, the patterning of polycides offers unique problems which the chemistries conventionally used for polysilicon dry etching do not meet; these chemistries do not maintain anisotropy for both the polysilicon and the refractory metal silicide such that the edges of the two layers in these composite films remain coincident. That is, for etching polycide films, it is desirable to have a single etchant gas mixture which will not only etch both materials, but will etch them so that the layered polycide structure has a predictably vertical edge afterwards.
The present invention not only solves the coincident edge etching requirements for polycide films, but also provides a method for patterning the full family of refractory metals, refractory metal silicides, and certain other metals.
The present invention teaches an integrated circuit plasma etching method which can be used to pattern interconnects using any metal or combination of metals which form volatile carbonyls and carbonyl halides over silicon dioxide or polysilicon, by etching the metal (or metal silicide) and (optionally) polysilicon anisotropically such that the polysilicon and refractory metal (or refractory metal silicide) layers have coincident edges.
In the prior art, polysilicon/refractory metal and metal silicide composite films were plasma or reactive ion etched using halogen chemistry. However, chlorine bearing gases, which etch polysilicon well, generally etch refractory metal or metal silicides at a slower rate. This results in undercut of the polysilicon layer of the polycide films. Other etch gas chemistries, based on fluorine-bearing gases, do provide coincident edges for the silicide and polysilicon layers in polycide films. However, such etching processes suffer from two disadvantages: first, they tend to be relatively isotropic, resulting in substantial line width narrowing of the etched film; second, they exhibit poor selectivity to silicon oxides. Thus, the use of halogen chemistries for plasma etching combinations of refractory metals or silicides with polysilicon is inadequate for mass production of VLSI integrated circuits.
The present invention solves these problems and provides a major advance in the art of plasma etching for fabrication of integrated circuits, by using plasma etch gas compositions which volatilize the metal fraction of interconnect layers as volatile metal carbonyls and/or carbonyl halides. Metal carbonyls and carbonyl halides have been used extensively in bulk chemical processing, and have been discussed extensively in the chemical literature, but the application of carbonyl chemistry to solve the unique problems which occur in etching of integrated circuits is believed not to have been suggested prior to the present invention.
The first metal carbonyl was discovered in 1890 when Mond, Langer, and Quinchy observed nickel carbonyl as the product of the reaction between nickel metal and carbon monoxide at 30 degrees centigrade. Since then, substantial study of carbonyls and carbonyl halides has led to a large number of publications and numerous applications for metal carbonyls. For example, nickel carbonyl has been used to deposit nickel thin films. Metal carbonyls have been used in refining titanium, zirconium, and hafnium. In organic synthesis, metal carbonyls have been used to stabilize systems that are normally unstable. A major application of metal carbonyls in organic chemistry is the use of nickel carbonyl in the synthesis of acrylates from acetylene and carbon monoxide.
That is, the existence of volatile carbonyl species is known in the chemical literature, but no known prior art teaches the patterned plasma etching of thin films using a carbonyl source gas. Similarly, the existence of the species gold carbonyl chloride (Au(COCl).sub.x) has been recently reported in the literature, but no known literature or other prior art teaches patterned plasma etching of thin films incorporating a metal component which can be volatilized as a carbonyl chloride.
The present invention provides a new advantageous class of integrated circuit etching processes, using halogen based gases (such as carbon tetrachloride, silicon tetrachloride, or a Freon.TM. such as CFCl.sub.3) with carbon monoxide or carbon dioxide in a plasma (or RIE) reactor to etch a metal or metal composite or compound by volatilization of the metal in the thin film as a carbonyl or carbonyl halide.
According to the present invention, there is provided: A method for patterning thin-film interconnects, comprising the steps of:
depositing a thin film of a composite layer structure comprising both polycrystalline silicon and a metal silicide on a predetermined substrate, having a patterned masking material in a predetermined pattern thereon; PA1 providing a reagent gas flow in proximity to said thin film of metal, said reagent gas flow including a carbonyl source gas; and PA1 applying rf power to create a plasma in proximity to said thin film of metal. PA1 depositing a thin film of a metal on a predetermined substrate, having a patterned masking material in a predetermined pattern thereon; PA1 providing a reagent gas flow in proximity to said thin film of metal, said reagent gas flow including a carbonyl source gas; and PA1 applying rf power to create a plasma in proximity to said thin film of metal. PA1 depositing a thin film of a metal silicide on a predetermined substrate, having a patterned masking material in a predetermined pattern thereon; PA1 providing a reagent gas flow in proximity to said thin film of metal silicide, said reagent gas flow including a carbonyl source gas; and PA1 applying rf power to create a plasma in proximity to said thin film of metal silicide. PA1 depositing a thin film of a composite layer structure comprising both polycrystalline silicon and a metal silicide on a predetermined substrate, having a patterned masking material in a predetermined pattern thereon; PA1 providing a reagent gas flow in proximity to said thin film of metal, said reagent gas flow including a halogen source and including a carbonyl source gas; and PA1 applying rf power to create a plasma in proximity to said thin film of metal.
According to the present invention, there is provided: A method for patterning thin-film metallization, comprising the steps of:
According to the present invention, there is provided: A method for patterning thin-film interconnects, comprising the steps of:
According to the present invention, there is provided: A method for patterning thin-film interconnects, comprising the steps of: